The present invention relates to a power saving technique for nonvolatile memory apparatuses, and more particularly to a technique that can be effectively applied to power consumption saving in nonvolatile semiconductor memories when in a standby mode.
As memory devices for use in personal computers and multi-functional terminal devices, memory cards such as multimedia cards are in rapidly spreading use. Some of the memory cards are dual voltage cards, operable on two or more different voltages.
As a type of semiconductor memory for use in such a memory card, there is a flash memory operable on two different power voltages (e.g. about 3.3 V and about 1.8 V).
Usually, a flash memory operable on two (or more) power voltages is provided with an internal logical circuit formed on a single semiconductor chip and operable on two different power voltages (e.g. about 3.3 V and about 1.8 V).
According to studies made by the present inventors, it is conceivable, for instance, to dispose within a flash memory a stepped-down power supply circuit, instead of providing an internal logical circuit operable on two (or more) power voltages and, where a power voltage of about 3.3 V is supplied, to step it down to a level of about 1.8 V with that stepped-down power supply circuit, and to supply the stepped-down voltage to the internal logical circuit as an internal power voltage.
Where that power voltage of about 1.8 V is supplied, that power voltage is directly supplied to the internal logical circuit as the internal power voltage.
Techniques described of a nonvolatile memory apparatus configured by using a stepped-down power supply circuit of this kind include one by which, when a load circuit is in a standby mode, data holding in the load circuit is secured by supplying a stepped-down voltage to that load circuit thereby to reduce power consumption (see Patent Reference 1), another by which power consumption in the step-down circuit in the standby mode, in which power consumption by internal circuits decreases, is reduced to save power consumption (see Patent Reference 2) and still another by which one regulator is used in different modes including a low voltage low current consumption mode and a high voltage high current consumption mode (see Patent Reference 3).
Patent Reference 1: Japanese Unexamined Patent Publication No. Hei 09(1997)-198151
Patent Reference 2: Japanese Unexamined Patent Publication No. Hei 10(1998)-74394
Patent Reference 3: Japanese Unexamined Patent Publication No. Hei 10(1998)-150152